Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`66 0F 58 /r` `ADDPD xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`sse2`	Add packed double-precision floating-point values from xmm1 and xmm2/m128. Store the result in xmm1.
Opcode: `66 0F 58 /r` Mnemonic: `ADDPD xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Add packed double-precision floating-point values from xmm1 and xmm2/m128. Store the result in xmm1.
`VEX.128.66.0F.WIG 58 /r` `VADDPD xmm1, xmm2, xmm3/m128`	`rvm`	Invalid	Valid	Valid	`avx`	Add packed double-precision floating-point values from xmm2 and xmm3/m128. Store the result in xmm1.
Opcode: `VEX.128.66.0F.WIG 58 /r` Mnemonic: `VADDPD xmm1, xmm2, xmm3/m128` Encoding: `rvm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Add packed double-precision floating-point values from xmm2 and xmm3/m128. Store the result in xmm1.
`VEX.256.66.0F.WIG 58 /r` `VADDPD ymm1, ymm2, ymm3/m256`	`rvm`	Invalid	Valid	Valid	`avx`	Add packed double-precision floating-point values from ymm2 and ymm3/m256. Store the result in ymm1.
Opcode: `VEX.256.66.0F.WIG 58 /r` Mnemonic: `VADDPD ymm1, ymm2, ymm3/m256` Encoding: `rvm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Add packed double-precision floating-point values from ymm2 and ymm3/m256. Store the result in ymm1.
`EVEX.128.66.0F.W1 58 /r` `VADDPD xmm1 {k1}{z}, xmm2, xmm3/m128/bcst64`	`ervm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Add packed double-precision floating-point values from xmm2 and xmm3/m128/bcst64. Store the result in xmm1.
Opcode: `EVEX.128.66.0F.W1 58 /r` Mnemonic: `VADDPD xmm1 {k1}{z}, xmm2, xmm3/m128/bcst64` Encoding: `ervm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Add packed double-precision floating-point values from xmm2 and xmm3/m128/bcst64. Store the result in xmm1.
`EVEX.256.66.0F.W1 58 /r` `VADDPD ymm1 {k1}{z}, ymm2, ymm3/m256/bcst64`	`ervm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Add packed double-precision floating-point values from ymm2 and ymm3/m256/bcst64. Store the result in ymm1.
Opcode: `EVEX.256.66.0F.W1 58 /r` Mnemonic: `VADDPD ymm1 {k1}{z}, ymm2, ymm3/m256/bcst64` Encoding: `ervm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Add packed double-precision floating-point values from ymm2 and ymm3/m256/bcst64. Store the result in ymm1.
`EVEX.512.66.0F.W1 58 /r` `VADDPD zmm1 {k1}{z}, zmm2, zmm3/m512/bcst64{er}`	`ervm`	Invalid	Valid	Valid	`avx512-f`	Add packed double-precision floating-point values from zmm2 and zmm3/m512/bcst64. Store the result in zmm1.
Opcode: `EVEX.512.66.0F.W1 58 /r` Mnemonic: `VADDPD zmm1 {k1}{z}, zmm2, zmm3/m512/bcst64{er}` Encoding: `ervm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Add packed double-precision floating-point values from zmm2 and zmm3/m512/bcst64. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3	Operand 4
`rm`	`n/a`	`ModRM.reg[rw]`	`ModRM.r/m[r]`
`rvm`	`n/a`	`ModRM.reg[rw]`	`VEX.vvvv[r]`	`ModRM.r/m[r]`
`ervm`	`full`	`ModRM.reg[rw]`	`EVEX.vvvvv[r]`	`ModRM.r/m[r]`

Description

The (V)ADDPD instruction adds two, four, or eight double-precision floating-point values from the two source operands. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void ADDPD(SimdF64 dest, SimdF64 src)
{
    dest[0] += src[0];
    dest[1] += src[1];
    // dest[2..] is unmodified
}

void VADDPD_Vex(SimdF64 dest, SimdF64 src1, SimdF64 src2, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = src1[n] + src2[n];
    dest[kl..] = 0;
}
public void VADDPD_Vex128(SimdF64 dest, SimdF64 src1, SimdF64 src2) =>
    VADDPD_Vex(dest, src1, src2, 2);
public void VADDPD_Vex256(SimdF64 dest, SimdF64 src1, SimdF64 src2) =>
    VADDPD_Vex(dest, src1, src2, 4);

void VADDPD_EvexMemory(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = src1[n] + (EVEX.b ? src2[0] : src2[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VADDPD_Evex128Memory(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexMemory(dest, src1, src2, k, 2);
public void VADDPD_Evex256Memory(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexMemory(dest, src1, src2, k, 4);
public void VADDPD_Evex512Memory(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexMemory(dest, src1, src2, k, 8);

void VADDPD_EvexRegister(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k, int kl)
{
    if (kl == 8 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = src1[n] + src2[n];
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VADDPD_Evex128Register(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexRegister(dest, src1, src2, k, 2);
public void VADDPD_Evex256Register(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexRegister(dest, src1, src2, k, 4);
public void VADDPD_Evex512Register(SimdF64 dest, SimdF64 src1, SimdF64 src2, KMask k) =>
    VADDPD_EvexRegister(dest, src1, src2, k, 8);

Intrinsics

__m128d _mm_add_pd(__m128d a, __m128d b)
__m128d _mm_mask_add_pd(__m128d s, __mmask8 k, __m128d a, __m128d b)
__m128d _mm_maskz_add_pd(__mmask8 k, __m128d a, __m128d b)

__m256d _mm256_add_pd(__m256d a, __m256d b)
__m256d _mm256_mask_add_pd(__m256d s, __mmask8 k, __m256d a, __m256d b)
__m256d _mm256_maskz_add_pd(__mmask8 k, __m256d a, __m256d b)

__m512d _mm512_add_pd(__m512d a, __m512d b)
__m512d _mm512_add_round_pd(__m512d a, __m512d b, const int rounding)
__m512d _mm512_mask_add_pd(__m512d s, __mmask8 k, __m512d a, __m512d b)
__m512d _mm512_mask_add_round_pd(__m512d s, __mmask8 k, __m512d a, __m512d b, const int rounding)
__m512d _mm512_maskz_add_pd(__mmask8 k, __m512d a, __m512d b)
__m512d _mm512_maskz_add_round_pd(__mmask8 k, __m512d a, __m512d b, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#D - Denormal operand.
#I - Invalid operation.
#O - Numeric overflow.
#P - Inexact result.
#U - Numeric underflow.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.