| Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
|---|---|---|---|---|---|---|
66 0F D0 /rADDSUBPD xmm1, xmm2/m128 | rm | Invalid | Valid | Valid | sse3 | Add/subtract packed double-precision floating-point values from xmm1 and xmm2/m128. Store the result in xmm1. |
VEX.128.66.0F.WIG D0 /rVADDSUBPD xmm1, xmm2, xmm3/m128 | rvm | Invalid | Valid | Valid | avx | Add/subtract packed double-precision floating-point values from xmm2 and xmm3/m128. Store the result in xmm1. |
VEX.256.66.0F.WIG D0 /rVADDSUBPD ymm1, ymm2, ymm3/m256 | rvm | Invalid | Valid | Valid | avx | Add/subtract packed double-precision floating-point values from ymm2 and ymm3/m256. Store the result in ymm1. |
Encoding
| Encoding | Operand 1 | Operand 2 | Operand 3 |
|---|---|---|---|
rm | ModRM.reg[rw] | ModRM.r/m[r] | |
rvm | ModRM.reg[rw] | VEX.vvvv[r] | ModRM.r/m[r] |
Description
The (V)ADDSUBPD instruction adds/subtracts double-precision floating-point value from the two source operands. The result is stored in the destination operand.
This instruction's "add/subtract" operation subtracts even offset and adds odd offset fields in the SIMD register.
All forms except the legacy SSE one will zero the upper (untouched) bits.
Operation
public void ADDSUBPD(SimdF64 dest, SimdF64 src)
{
dest[0] -= src[0];
dest[1] += src[1];
// dest[2..] is unmodified
}
public void VADDSUBPD_Vex128(SimdF64 dest, SimdF64 src1, SimdF64 src2)
{
dest[0] -= src[0];
dest[1] += src[1];
dest[2..] = 0;
}
public void VADDSUBPD_Vex256(SimdF64 dest, SimdF64 src1, SimdF64 src2)
{
dest[0] -= src[0];
dest[1] += src[1];
dest[2] -= src[2];
dest[3] += src[3];
dest[4..] = 0;
}Intrinsics
__m128d _mm_addsub_pd(__m128d a, __m128d b)
__m256d _mm256_addsub_pd(__m256d a, __m256d b)Exceptions
SIMD Floating-Point
#XM#D- Denormal operand.#I- Invalid operation.#O- Numeric overflow.#P- Inexact result.#U- Numeric underflow.
Other Exceptions
VEX Encoded Form: See Type 2 Exception Conditions.
#GP(0)- If a memory operand is not aligned to a
- 16-byte
- boundary.