Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
---|---|---|---|---|---|---|
66 0F 38 DB /r AESIMC xmm1, xmm2/m128 | rm | Invalid | Valid | Valid | aes | Perform the "inverse mix columns" transformation on a 128 bit round key in xmm2/m128. Store the result in xmm1. |
VEX.128.66.0F38.WIG DB /r VAESIMC xmm1, xmm2/m128 | rm | Invalid | Valid | Valid | avx aes | Perform the "inverse mix columns" transformation on a 128 bit round key in xmm2/m128. Store the result in xmm1. |
Encoding
Encoding | Operand 1 | Operand 2 |
---|---|---|
rm | ModRM.reg[w] | ModRM.r/m[r] |
Description
The (V)AESIMC
instruction performs the "inverse mix columns" transformation on a round key stored in the source operand. The result is stored in in the destination operand.
This instruction should be applied to the expanded AES round keys (excepting the first and last) to prepare them for decryption using the "Equivalent Inverse Cipher" (see FIPS 197).
VEX.vvvv
is reserved and must be b1111
(0
inverted). Any other values will raise a #UD
exception. All forms except the legacy SSE one will zero the upper (untouched) bits.
Operation
public void AESIMC(SimdU128 dest, SimdU128 src)
{
dest[0] = AesInvMixColumns(src[0]);
// dest[1..] is unmodified
}
public void VAESIMC_Vex128(SimdU128 dest, SimdU128 src)
{
dest[0] = AesInvMixColumns(src[0]);
dest[1..] = 0;
}
Intrinsics
__m128i _mm_aesimc(__m128i)
Exceptions
SIMD Floating-Point
None.Other Exceptions
VEX Encoded Form: See Type 4 Exception Conditions.
#UD
- If
VEX.vvvv
- is not
1111b
- .