Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
---|---|---|---|---|---|---|
VEX.L0.NP.0F38.W0 F2 /r ANDN r32a, r32b, r/m32 | rvm | Invalid | Valid | Valid | bmi1 | Logical AND r32b (inverted) and r/m32. Store the result in r32a. |
VEX.L0.NP.0F38.W1 F2 /r ANDN r64a, r64b, r/m64 | rvm | Invalid | Invalid | Valid | bmi1 | Logical AND r64b (inverted) and r/m64. Store the result in r64a. |
Encoding
Encoding | Operand 1 | Operand 2 | Operand 3 |
---|---|---|---|
rvm | ModRM.reg[w] | VEX.vvvv[r] | ModRM.r/m[r] |
Description
The ANDN
instruction ANDs the two source operands. The first source operand is inverted before being ANDed with the other source operand. The result is stored in the destination operand.
The operand size is always 32 bits if not in Long Mode. In other words, VEX.W1
is treated as VEX.W0
outside Long Mode.
Operation
public void ANDN(ref U32 dest, U32 src1, U32 src2)
{
dest = ~src1 & src2;
}
public void ANDN(ref U64 dest, U64 src1, U64 src2)
{
dest = ~src1 & src2;
}
Flags Affected
CF
(carry flag)- Cleared.
PF
(parity flag)- Undefined.
AF
(auxiliary flag)- Undefined.
ZF
(zero flag)- Set according to the result.
SF
(sign flag)- Set according to the result.
OF
(overflow flag)- Cleared.
Intrinsics
None. Auto-generated by compiler.
Exceptions
SIMD Floating-Point
None.Other Exceptions
VEX Encoded Form: See Type 13 Exception Conditions.