Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
---|---|---|---|---|---|---|
VEX.L0.NP.0F38.W0 F7 /r BEXTR r32a, r/m32, r32b | rmv | Invalid | Valid | Valid | bmi1 | Contiguous bitwise extract from r/m32 using r32b as a control. Store the result in r32a. |
VEX.L0.NP.0F38.W1 F7 /r BEXTR r64a, r/m64, r64b | rmv | Invalid | Invalid | Valid | bmi1 | Contiguous bitwise extract from r/m64 using r64b as a control. Store the result in r64a. |
XOP.L0.NP.0A.W0 10 /r id BEXTR r32, r/m32, imm32 | rmi | Invalid | Valid | Valid | tbm | Contiguous bitwise extract from r/m32 using imm32 as a control. Store the result in r32. |
XOP.L0.NP.0A.W1 10 /r id BEXTR r64, r/m64, imm32 | rmi | Invalid | Invalid | Valid | tbm | Contiguous bitwise extract from r/m64 using imm32 as a control. Store the result in r64. |
Encoding
Encoding | Operand 1 | Operand 2 | Operand 3 |
---|---|---|---|
rmv | ModRM.reg[w] | ModRM.r/m[r] | VEX.vvvv[r] |
rmi | ModRM.reg[w] | ModRM.r/m[r] | imm32 |
Description
The BEXTR
instruction extracts contiguous bits from the first source operand using using index and length values provided in the second source operand. The result is stored in the destination operand.
The control register contains 16 bits: the lower eight are the starting index into the slice, and the upper eight is the amount of bits to extract. In other words, the destination register will be filled least significant to most significant by copying from the source, beginning at the starting position (where 0 indicates the least significant bit). The length field determines how many bits are extracted. Bits 16..
of the control operand are ignored.
The operand size is always 32 bits if not in Long Mode. In other words, VEX.W1
and XOP.W1
are treated as VEX.W0
and XOP.W0
(respectively) outside Long Mode.
Operation
public void BEXTR(ref U32 dest, U32 src1, U32 src2)
{
// both VEX and XOP forms
U8 start = src2[0..7];
U8 end = start + src2[8..15];
dest = src1[start..end];
}
public void BEXTR(ref U64 dest, U64 src1, U32 src2)
{
// XOP form
BEXTR(ref dest, src1, (U64)src2);
}
public void BEXTR(ref U64 dest, U64 src1, U64 src2)
{
// VEX form
U8 start = src2[0..7];
U8 end = start + src2[8..15];
dest = src1[start..end]
}
Flags Affected
CF
(carry flag)- Cleared.
PF
(parity flag)- Undefined.
AF
(auxiliary flag)- Undefined.
ZF
(zero flag)- Set according to the result.
SF
(sign flag)- Undefined.
OF
(overflow flag)- Cleared.
Intrinsics
uint32_t _bextr_u32(uint32_t src, uint32_t start, uint32_t len)
uint64_t _bextr_u64(uint64_t src, uint32_t start, uint32_t len)
Exceptions
SIMD Floating-Point
None.Other Exceptions
VEX Encoded Form: See Type 13 Exception Conditions.