| Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
|---|---|---|---|---|---|---|
66 0F 3A 0D /r ibBLENDPD xmm1, xmm2/m128, imm8 | rmi | Invalid | Valid | Valid | sse4.1 | Select packed double-precision floating-point values from xmm1 and xmm2/m128 using a mask specified in imm8. Store the result in xmm1. |
VEX.128.66.0F3A.WIG 0D /r ibVBLENDPD xmm1, xmm2, xmm3/m128, imm8 | rvmi | Invalid | Valid | Valid | avx | Select packed double-precision floating-point values from xmm2 and xmm3/m128 using a mask specified in imm8. Store the result in xmm1. |
VEX.256.66.0F3A.WIG 0D /r ibVBLENDPD ymm1, ymm2, ymm3/m256, imm8 | rvmi | Invalid | Valid | Valid | avx | Select packed double-precision floating-point values from ymm2 and ymm3/m128 using a mask specified in imm8. Store the result in ymm1. |
Encoding
| Encoding | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
rmi | ModRM.reg[rw] | ModRM.r/m[r] | imm8 | |
rvmi | ModRM.reg[w] | VEX.vvvv[r] | ModRM.r/m[r] | imm8 |
Description
The (V)BLENDPD instruction conditionally moves double-precision floating-point values from the two source operands. From the control byte, each bit, if cleared, will move from the first source operand, and, if set, will move from the second source operand. The result is stored in the destination operand.
This instruction, despite being named as if it operates on floating-point numbers, will work on 64-bit integers as well.
All forms except the legacy SSE one will zero the upper (untouched) bits.
Operation
public void BLENDPD(SimdF64 dest, SimdF64 src, U8 mask)
{
// if `mask.Bit[n]` is 0, `dest` will be copied into itself (i.e. nothing happens)
if (mask.Bit[0])
dest[0] = src[0];
if (mask.Bit[1])
dest[1] = src[1];
// dest[2..] is unmodified
}
void VBLENDPD_Vex(SimdF64 dest, SimdF64 src1, SimdF64 src2, U8 mask, int kl)
{
for (int n = 0; n < kl; n++)
dest[n] = mask.Bit[n] ? src2[n] : src1[n];
dest[kl..] = 0;
}
public void VBLENDPD_Vex128(SimdF64 dest, SimdF64 src1, SimdF64 src2, U8 mask) =>
VBLENDPD_Vex(dest, src1, src2, mask, 2);
public void VBLENDPD_Vex256(SimdF64 dest, SimdF64 src1, SimdF64 src2, U8 mask) =>
VBLENDPD_Vex(dest, src1, src2, mask, 4);Intrinsics
__m128d _mm_blend_pd(__m128d v1, __m128d v2, const uint32_t mask)
__m256d _mm256_blend_pd(__m256d a, __m256d b, const uint32_t mask)Exceptions
SIMD Floating-Point
None.Other Exceptions
VEX Encoded Form: See Type 4 Exception Conditions.