| Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
|---|---|---|---|---|---|---|
66 0F 38 14 /r ibBLENDVPS xmm1, xmm2/m128, XMM0 | rm | Invalid | Valid | Valid | sse4.1 | Select packed single-precision floating-point values from xmm1 and xmm2/m128 using a mask specified in XMM0. Store the result in xmm1. |
VEX.128.66.0F3A.W0 4A /r /is4VBLENDVPS xmm1, xmm2, xmm3/m128, xmm4 | rvmb | Invalid | Valid | Valid | avx | Select packed single-precision floating-point values from xmm2 and xmm3/m128 using a mask specified in xmm4. Store the result in xmm1. |
VEX.256.66.0F3A.W0 4A /r /is4VBLENDVPS ymm1, ymm2, ymm3/m256, ymm4 | rvmb | Invalid | Valid | Valid | avx | Select packed single-precision floating-point values from ymm2 and ymm3/m128 using a mask specified in ymm4. Store the result in ymm1. |
Encoding
| Encoding | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
|---|---|---|---|---|
rm | ModRM.reg[rw] | ModRM.r/m[r] | XMM0 | |
rvmb | ModRM.reg[w] | VEX.vvvv[r] | ModRM.r/m[r] | imm8(4..7) |
Description
The (V)BLENDVPS instruction conditionally moves single-precision floating-point values from the two source operands. From the control operand, each bit, if cleared, will move from the first source operand, and, if set, will move from the second source operand. The result is stored in the destination operand.
This instruction, despite being named as if it operates on floating-point numbers, will work on 64-bit integers as well.
All forms except the legacy SSE one will zero the upper (untouched) bits.
Operation
public void BLENDVPS(SimdF32 dest, SimdF32 src)
{
// if `XMM0.Bit[n]` is 0, `dest` will be copied into itself (i.e. nothing happens)
if (XMM0.Bit[0])
dest[0] = src[0];
if (XMM0.Bit[1])
dest[1] = src[1];
if (XMM0.Bit[2])
dest[2] = src[2];
if (XMM0.Bit[3])
dest[3] = src[3];
// dest[4..] is unmodified
}
void VBLENDVPS_Vex(SimdF32 dest, SimdF32 src1, SimdF32 src2, SimdF32 mask, int kl)
{
for (int n = 0; n < kl; n++)
dest[n] = mask.Bit[n] ? src2[n] : src1[n];
dest[kl..] = 0;
}
public void VBLENDVPS_Vex128(SimdF32 dest, SimdF32 src1, SimdF32 src2, SimdF32 mask) =>
VBLENDVPS_Vex(dest, src1, src2, mask, 4);
public void VBLENDVPS_Vex256(SimdF32 dest, SimdF32 src1, SimdF32 src2, SimdF32 mask) =>
VBLENDVPS_Vex(dest, src1, src2, mask, 8);Intrinsics
__m128 _mm_blendv_ps(__m128d a, __m128d b, __m128d mask)
__m256 _mm256_blendv_ps(__m256d a, __m256d b, __m256d mask)Exceptions
SIMD Floating-Point
None.Other Exceptions
VEX Encoded Form: See Type 4 Exception Conditions.
#UD- If
VEX.W- is not
0- .