Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`66 0F 5A /r` `CVTPD2PS xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`sse2`	Convert packed double-precision floating-point values from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `66 0F 5A /r` Mnemonic: `CVTPD2PS xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert packed double-precision floating-point values from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
`VEX.128.66.0F.WIG 5A /r` `VCVTPD2PS xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed double-precision floating-point values from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `VEX.128.66.0F.WIG 5A /r` Mnemonic: `VCVTPD2PS xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed double-precision floating-point values from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
`VEX.256.66.0F.WIG 5A /r` `VCVTPD2PS ymm1, ymm2/m256`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed double-precision floating-point values from ymm2/m256 into packed single-precision floating-point values. Store the result in ymm1.
Opcode: `VEX.256.66.0F.WIG 5A /r` Mnemonic: `VCVTPD2PS ymm1, ymm2/m256` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed double-precision floating-point values from ymm2/m256 into packed single-precision floating-point values. Store the result in ymm1.
`EVEX.128.66.0F.W1 5A /r` `VCVTPD2PS xmm1 {k1}{z}, xmm2/m128/m64bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed double-precision floating-point values from xmm2/m128/m64bcst into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `EVEX.128.66.0F.W1 5A /r` Mnemonic: `VCVTPD2PS xmm1 {k1}{z}, xmm2/m128/m64bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed double-precision floating-point values from xmm2/m128/m64bcst into packed single-precision floating-point values. Store the result in xmm1.
`EVEX.256.66.0F.W1 5A /r` `VCVTPD2PS ymm1 {k1}{z}, ymm2/m256/m64bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed double-precision floating-point values from ymm2/m256/m64bcst into packed single-precision floating-point values. Store the result in ymm1.
Opcode: `EVEX.256.66.0F.W1 5A /r` Mnemonic: `VCVTPD2PS ymm1 {k1}{z}, ymm2/m256/m64bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed double-precision floating-point values from ymm2/m256/m64bcst into packed single-precision floating-point values. Store the result in ymm1.
`EVEX.512.66.0F.W1 5A /r` `VCVTPD2PS zmm1 {k1}{z}, zmm2/m512/m64bcst{er}`	`erm`	Invalid	Valid	Valid	`avx512-f`	Convert packed double-precision floating-point values from zmm2/m512/m64bcst into packed single-precision floating-point values. Store the result in zmm1.
Opcode: `EVEX.512.66.0F.W1 5A /r` Mnemonic: `VCVTPD2PS zmm1 {k1}{z}, zmm2/m512/m64bcst{er}` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert packed double-precision floating-point values from zmm2/m512/m64bcst into packed single-precision floating-point values. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`erm`	`full`	`ModRM.reg[w]`	`ModRM.r/m[r]`

Description

The (V)CVTPD2PS instruction converts two, four, or eight double-precision floating-point values from the source operand into single-precision floating-point values. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void CVTPD2PS(SimdF32 dest, SimdF64 src)
{
    dest[0] = ConvertToF32(src[0]);
    dest[1] = ConvertToF32(src[1]);
    // dest[2..] is unmodified
}

void VCVTPD2PS_Vex(SimdF32 dest, SimdF64 src, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = ConvertToF32(src[n]);
    dest[kl..] = 0;
}
public void VCVTPD2PS_Vex128(SimdF32 dest, SimdF64 src) =>
    VCVTPD2PS_Vex(dest, src, 2);
public void VCVTPD2PS_Vex256(SimdF32 dest, SimdF64 src) =>
    VCVTPD2PS_Vex(dest, src, 4);

void VCVTPD2PS_EvexMemory(SimdF32 dest, SimdF64 src, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF32(EVEX.b ? src[0] : src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPD2PS_Evex128Memory(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemory(dest, src, k, 2);
public void VCVTPD2PS_Evex256Memory(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemory(dest, src, k, 4);
public void VCVTPD2PS_Evex512Memory(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemory(dest, src, k, 8);

void VCVTPD2PS_EvexRegister(SimdF32 dest, SimdF64 src, KMask k, int kl)
{
    if (kl == 8 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF32(src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPD2PS_Evex128Register(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemoryRegister(dest, src, k, 2);
public void VCVTPD2PS_Evex256Register(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemoryRegister(dest, src, k, 4);
public void VCVTPD2PS_Evex512Register(SimdF32 dest, SimdF64 src, KMask k) =>
    VCVTPD2PS_EvexMemoryRegister(dest, src, k, 8);

Intrinsics

__m128i _mm_cvtpd_ps(__m128d src)
__m128i _mm_mask_cvtpd_ps(__m128i s, __mmask8 k, __m128d a)
__m128i _mm_maskz_cvtpd_ps(__mmask8 k, __m128d a)

__m128i _mm256_cvtpd_ps(__m256d src)
__m128i _mm256_mask_cvtpd_ps(__m128i s, __mmask8 k, __m256d a)
__m128i _mm256_maskz_cvtpd_ps(__mmask8 k, __m256d a)

__m256i _mm512_cvtpd_ps(__m512d a)
__m256i _mm512_cvt_roundpd_ps(__m512d a, const int rounding)
__m256i _mm512_mask_cvtpd_ps(__m256i s, __mmask8 k, __m512d a)
__m256i _mm512_mask_cvt_roundpd_ps(__m256i s, __mmask8 k, __m512d a, const int rounding)
__m256i _mm512_maskz_cvtpd_ps(__mmask8 k, __m512d a)
__m256i _mm512_maskz_cvt_roundpd_ps(__mmask8 k, __m512d a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#D - Denormal operand.
#I - Invalid operation.
#O - Numeric overflow.
#P - Inexact result.
#U - Numeric underflow.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.