Flush Cache Line

Encoding

Description

The CLFLUSH instruction invalidates every level of the cache hierarchy containing the operand's effective address. This will force any "dirty" memory in the caches to be written back to main memory.

Executions of this instruction are ordered with respect to each other, writes, locked RMW (read‑modify‑write), and "fence" instructions. However, they are not ordered with respect to executions of CLFLUSHOPT (Flush Cache Line (Optimized)) and CLWB (Write Back Cache Line).

In some architectures, this instruction may cause a transactional abort with the Transactional Synchronization Extensions (TSX). However, programmers must not rely on this behavior.

Operation

public void CLFLUSH(IntPtr addr)
{
    CacheLineFlush(addr);
}

Intrinsics

void _mm_clflush(const void *ptr)

Exceptions

Real-Address Mode

Virtual-8086 Mode

Protected Mode

Compatibility Mode

Long Mode