Compare Ordered Scalar Double-Precision Floating-Point Value and Set EFLAGS

Encoding

Description

The (V)COMISD instruction compares a single double-precision floating-point values from the two source operands. The flags are updated (per logic below) and the result discarded.

The result of the comparison is indicated using EFLAGS.ZF, EFLAGS.PF, and EFLAGS.CF in a way that does not match their names. The resulting values in the flags is detailed in this table:

1. If either operand is NaN.

Operation

public void COMISD(SimdF64 src1, SimdF64 src2)
{
    _ = OrderedCompare(src1[0], src2[0]);
}

public void VCOMISD_Vex(SimdF64 src1, SimdF64 src2) =>
    COMISD(src1, src2);

public void VCOMISD_Evex(SimdF64 src1, SimdF64 src2) =>
    COMISD(src1, src2);

Flags Affected

CF (carry flag)

Set if the first source operand is less than the second, or if either operand is NaN. Cleared otherwise.

PF (parity flag)

Set if either operand is NaN. Cleared otherwise.

AF (auxiliary flag)

Cleared.

ZF (zero flag)

Set if both operands are equal, or if either operand is NaN. Cleared otherwise.

SF (sign flag)

Cleared.

OF (overflow flag)

Cleared.

Intrinsics

int _mm_comilt_sd(__m128 a, __m128 b)
int _mm_comile_sd(__m128 a, __m128 b)
int _mm_comieq_sd(__m128 a, __m128 b)
int _mm_comige_sd(__m128 a, __m128 b)
int _mm_comigt_sd(__m128 a, __m128 b)
int _mm_comineq_sd(__m128 a, __m128 b)
int _mm_comi_round_sd(__m128 a, __m128 b, int predicate, int sae)

Exceptions

SIMD Floating-Point

Other Exceptions

VEX Encoded Form: See Type 3 Exception Conditions.
EVEX Encoded Form: See Type E3 Exception Conditions.