Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`NP 0F 5B /r` `CVTDQ2PS xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`sse2`	Convert packed doubleword integers from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `NP 0F 5B /r` Mnemonic: `CVTDQ2PS xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert packed doubleword integers from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
`VEX.128.NP.0F.WIG 5B /r` `VCVTDQ2PS xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed doubleword integers from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `VEX.128.NP.0F.WIG 5B /r` Mnemonic: `VCVTDQ2PS xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed doubleword integers from xmm2/m128 into packed single-precision floating-point values. Store the result in xmm1.
`VEX.256.NP.0F.WIG 5B /r` `VCVTDQ2PS ymm1, ymm2/m256`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed doubleword integers from ymm2/m256 into packed single-precision floating-point values. Store the result in ymm1.
Opcode: `VEX.256.NP.0F.WIG 5B /r` Mnemonic: `VCVTDQ2PS ymm1, ymm2/m256` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed doubleword integers from ymm2/m256 into packed single-precision floating-point values. Store the result in ymm1.
`EVEX.128.NP.0F.W0 5B /r` `VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed doubleword integers from xmm2/m128/m32bcst into packed single-precision floating-point values. Store the result in xmm1.
Opcode: `EVEX.128.NP.0F.W0 5B /r` Mnemonic: `VCVTDQ2PS xmm1 {k1}{z}, xmm2/m128/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed doubleword integers from xmm2/m128/m32bcst into packed single-precision floating-point values. Store the result in xmm1.
`EVEX.256.NP.0F.W0 5B /r` `VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed doubleword integers from ymm2/m256/m32bcst into packed single-precision floating-point values. Store the result in ymm1.
Opcode: `EVEX.256.NP.0F.W0 5B /r` Mnemonic: `VCVTDQ2PS ymm1 {k1}{z}, ymm2/m256/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed doubleword integers from ymm2/m256/m32bcst into packed single-precision floating-point values. Store the result in ymm1.
`EVEX.512.NP.0F.W0 5B /r` `VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}`	`erm`	Invalid	Valid	Valid	`avx512-f`	Convert packed doubleword integers from zmm2/m512/m32bcst into packed single-precision floating-point values. Store the result in zmm1.
Opcode: `EVEX.512.NP.0F.W0 5B /r` Mnemonic: `VCVTDQ2PS zmm1 {k1}{z}, zmm2/m512/m32bcst{er}` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert packed doubleword integers from zmm2/m512/m32bcst into packed single-precision floating-point values. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`erm`	`full`	`ModRM.reg[w]`	`ModRM.r/m[r]`

Description

The (V)CVTDQ2PS instruction converts four, eight, or 16 doubleword integers from the source operand into single-precision floating-point values. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void CVTDQ2PS(SimdF32 dest, SimdI32 src)
{
    dest[0] = ConvertToF32(src[0]);
    dest[1] = ConvertToF32(src[1]);
    dest[2] = ConvertToF32(src[2]);
    dest[3] = ConvertToF32(src[3]);
    // dest[4..] is unmodified
}

void VCVTDQ2PS_Vex(SimdF32 dest, SimdI32 src, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = ConvertToF32(src[n]);
    dest[kl..] = 0;
}
public void VCVTDQ2PS_Vex128(SimdF32 dest, SimdI32 src) =>
    VCVTDQ2PS_Vex(dest, src, 4);
public void VCVTDQ2PS_Vex128(SimdF32 dest, SimdI32 src) =>
    VCVTDQ2PS_Vex(dest, src, 8);

void VCVTDQ2PS_EvexMemory(SimdF32 dest, SimdI32 src, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF32(EVEX.b ? src[0] : src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTDQ2PS_Evex128Memory(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexMemory(dest, src, k, 4);
public void VCVTDQ2PS_Evex256Memory(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexMemory(dest, src, k, 8);
public void VCVTDQ2PS_Evex512Memory(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexMemory(dest, src, k, 16);

void VCVTDQ2PS_EvexRegister(SimdF32 dest, SimdI32 src, KMask k, int kl)
{
    if (kl == 16 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF32(src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTDQ2PS_Evex128Register(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexRegister(dest, src, k, 4);
public void VCVTDQ2PS_Evex256Register(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexRegister(dest, src, k, 8);
public void VCVTDQ2PS_Evex512Register(SimdF32 dest, SimdI32 src, KMask k) =>
    VCVTDQ2PS_EvexRegister(dest, src, k, 16);

Intrinsics

__m128 _mm_cvtepi32_ps(__m128i src)
__m128 _mm_mask_cvtepi32_ps(__m128 s, __mmask8 k, __m128i a)
__m128 _mm_maskz_cvtepi32_ps(__mmask8 k, __m128i a)

__m256 _mm256_cvtepi32_ps(__m256i src)
__m256 _mm256_mask_cvtepi32_ps(__m256 s, __mmask8 k, __m256i a)
__m256 _mm256_maskz_cvtepi32_ps(__mmask8 k, __m256i a)

__m512 _mm512_cvtepi32_ps(__m512i a)
__m512 _mm512_cvt_roundepi32_ps(__m512i a, const int rounding)
__m512 _mm512_mask_cvtepi32_ps(__m512 s, __mmask16 k, __m512i a)
__m512 _mm512_mask_cvt_roundepi_ps(__m512 s, __mmask16 k, __m512i a, const int rounding)
__m512 _mm512_maskz_cvtepi32_ps(__mmask16 k, __m512i a)
__m512 _mm512_maskz_cvt_roundepi32_ps(__mmask16 k, __m512i a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#P - Inexact result.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.