Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`F2 0F E6 /r` `CVTPD2DQ xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`sse2`	Convert packed double-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
Opcode: `F2 0F E6 /r` Mnemonic: `CVTPD2DQ xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert packed double-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
`VEX.128.F2.0F.WIG E6 /r` `VCVTPD2DQ xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed double-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
Opcode: `VEX.128.F2.0F.WIG E6 /r` Mnemonic: `VCVTPD2DQ xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed double-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
`VEX.256.F2.0F.WIG E6 /r` `VCVTPD2DQ ymm1, ymm2/m256`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed double-precision floating-point values from ymm2/m256 into packed doubleword integers. Store the result in ymm1.
Opcode: `VEX.256.F2.0F.WIG E6 /r` Mnemonic: `VCVTPD2DQ ymm1, ymm2/m256` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed double-precision floating-point values from ymm2/m256 into packed doubleword integers. Store the result in ymm1.
`EVEX.128.F2.0F.W1 E6 /r` `VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed double-precision floating-point values from xmm2/m128/m64bcst into packed doubleword integers. Store the result in xmm1.
Opcode: `EVEX.128.F2.0F.W1 E6 /r` Mnemonic: `VCVTPD2DQ xmm1 {k1}{z}, xmm2/m128/m64bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed double-precision floating-point values from xmm2/m128/m64bcst into packed doubleword integers. Store the result in xmm1.
`EVEX.256.F2.0F.W1 E6 /r` `VCVTPD2DQ ymm1 {k1}{z}, ymm2/m256/m64bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed double-precision floating-point values from ymm2/m256/m64bcst into packed doubleword integers. Store the result in ymm1.
Opcode: `EVEX.256.F2.0F.W1 E6 /r` Mnemonic: `VCVTPD2DQ ymm1 {k1}{z}, ymm2/m256/m64bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed double-precision floating-point values from ymm2/m256/m64bcst into packed doubleword integers. Store the result in ymm1.
`EVEX.512.F2.0F.W1 E6 /r` `VCVTPD2DQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er}`	`erm`	Invalid	Valid	Valid	`avx512-f`	Convert packed double-precision floating-point values from zmm2/m512/m64bcst into packed doubleword integers. Store the result in zmm1.
Opcode: `EVEX.512.F2.0F.W1 E6 /r` Mnemonic: `VCVTPD2DQ zmm1 {k1}{z}, zmm2/m512/m64bcst{er}` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert packed double-precision floating-point values from zmm2/m512/m64bcst into packed doubleword integers. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`erm`	`full`	`ModRM.reg[w]`	`ModRM.r/m[r]`

Description

The(V)CVTPD2DQ instruction converts two, four, or eight double - precision floating - point values from the source operand into doubleword integers. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void CVTPD2DQ(SimdI32 dest, SimdF64 src)
{
    dest[0] = ConvertToI32(src[0]);
    dest[1] = ConvertToI32(src[1]);
    // dest[2..] is unmodified
}

void VCVTPD2DQ_Vex(SimdI32 dest, SimdF64 src, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = ConvertToI32(src[n]);
    dest[kl..] = 0;
}
public void VCVTPD2DQ_Vex128(SimdI32 dest, SimdF64 src) =>
    VCVTPD2DQ_Vex(dest, src, 2);
public void VCVTPD2DQ_Vex256(SimdI32 dest, SimdF64 src) =>
    VCVTPD2DQ_Vex(dest, src, 4);

void VCVTPD2DQ_EvexMemory(SimdI32 dest, SimdF64 src, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToI32(EVEX.b ? src[0] : src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPD2DQ_Evex128Memory(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexMemory(dest, src, k, 2);
public void VCVTPD2DQ_Evex256Memory(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexMemory(dest, src, k, 4);
public void VCVTPD2DQ_Evex512Memory(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexMemory(dest, src, k, 8);

void VCVTPD2DQ_EvexRegister(SimdI32 dest, SimdF64 src, KMask k, int kl)
{
    if (kl == 8 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToI32(src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPD2DQ_Evex128Register(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexRegister(dest, src, k, 2);
public void VCVTPD2DQ_Evex256Register(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexRegister(dest, src, k, 4);
public void VCVTPD2DQ_Evex512Register(SimdI32 dest, SimdF64 src, KMask k) =>
    VCVTPD2DQ_EvexRegister(dest, src, k, 8);

Intrinsics

__m128i _mm_cvtpd_epi32(__m128d src)
__m128i _mm_mask_cvtpd_epi32(__m128i s, __mmask8 k, __m128d a)
__m128i _mm_maskz_cvtpd_epi32(__mmask8 k, __m128d a)

__m128i _mm256_cvtpd_epi32(__m256d src)
__m128i _mm256_mask_cvtpd_epi32(__m128i s, __mmask8 k, __m256d a)
__m128i _mm256_maskz_cvtpd_epi32(__mmask8 k, __m256d a)

__m256i _mm512_cvtpd_epi32(__m512d a)
__m256i _mm512_cvt_roundpd_epi32(__m512d a, const int rounding)
__m256i _mm512_mask_cvtpd_epi32(__m256i s, __mmask8 k, __m512d a)
__m256i _mm512_mask_cvt_roundpd_epi32(__m256i s, __mmask8 k, __m512d a, const int rounding)
__m256i _mm512_maskz_cvtpd_epi32(__mmask8 k, __m512d a)
__m256i _mm512_maskz_cvt_roundpd_epi32(__mmask8 k, __m512d a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#I - Invalid operation.
#P - Inexact result.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.