Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`66 0F 5B /r` `CVTPS2DQ xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`sse2`	Convert packed single-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
Opcode: `66 0F 5B /r` Mnemonic: `CVTPS2DQ xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert packed single-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
`VEX.128.66.0F.WIG 5B /r` `VCVTPS2DQ xmm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed single-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
Opcode: `VEX.128.66.0F.WIG 5B /r` Mnemonic: `VCVTPS2DQ xmm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed single-precision floating-point values from xmm2/m128 into packed doubleword integers. Store the result in xmm1.
`VEX.256.66.0F.WIG 5B /r` `VCVTPS2DQ ymm1, ymm2/m256`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed single-precision floating-point values from ymm2/m256 into packed doubleword integers. Store the result in ymm1.
Opcode: `VEX.256.66.0F.WIG 5B /r` Mnemonic: `VCVTPS2DQ ymm1, ymm2/m256` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed single-precision floating-point values from ymm2/m256 into packed doubleword integers. Store the result in ymm1.
`EVEX.128.66.0F.W0 5B /r` `VCVTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed single-precision floating-point values from xmm2/m128/m32bcst into packed doubleword integers. Store the result in xmm1.
Opcode: `EVEX.128.66.0F.W0 5B /r` Mnemonic: `VCVTPS2DQ xmm1 {k1}{z}, xmm2/m128/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed single-precision floating-point values from xmm2/m128/m32bcst into packed doubleword integers. Store the result in xmm1.
`EVEX.256.66.0F.W0 5B /r` `VCVTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed single-precision floating-point values from ymm2/m256/m32bcst into packed doubleword integers. Store the result in ymm1.
Opcode: `EVEX.256.66.0F.W0 5B /r` Mnemonic: `VCVTPS2DQ ymm1 {k1}{z}, ymm2/m256/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed single-precision floating-point values from ymm2/m256/m32bcst into packed doubleword integers. Store the result in ymm1.
`EVEX.512.66.0F.W0 5B /r` `VCVTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er}`	`erm`	Invalid	Valid	Valid	`avx512-f`	Convert packed single-precision floating-point values from zmm2/m512/m32bcst into packed doubleword integers. Store the result in zmm1.
Opcode: `EVEX.512.66.0F.W0 5B /r` Mnemonic: `VCVTPS2DQ zmm1 {k1}{z}, zmm2/m512/m32bcst{er}` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert packed single-precision floating-point values from zmm2/m512/m32bcst into packed doubleword integers. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`erm`	`full`	`ModRM.reg[w]`	`ModRM.r/m[r]`

Description

The (V)CVTPS2DQ instruction converts four, eight, or 16 single-precision floating-point values from the source operand into doubleword integers. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void CVTPS2DQ(SimdI32 dest, SimdF32 src)
{
    dest[0] = ConvertToI32(src[0]);
    dest[1] = ConvertToI32(src[1]);
    dest[2] = ConvertToI32(src[2]);
    dest[3] = ConvertToI32(src[3]);
    // dest[4..] is unmodified
}

void VCVTPS2DQ_Vex(SimdI32 dest, SimdF32 src, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = ConvertToI32(src[n]);
    dest[kl..] = 0;
}
public void VCVTPS2DQ_Vex128(SimdI32 dest, SimdF32 src) =>
    VCVTPS2DQ_Vex(dest, src, 4);
public void VCVTPS2DQ_Vex256(SimdI32 dest, SimdF32 src) =>
    VCVTPS2DQ_Vex(dest, src, 8);

void VCVTPS2DQ_EvexMemory(SimdI32 dest, SimdF32 src, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToI32(EVEX.b ? src[0] : src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPS2DQ_Evex128(SimdI32 dest, SimdF32 src, KMask k) =>
    VCVTPS2DQ_EvexMemory(dest, src, k, 4);
public void VCVTPS2DQ_Evex256(SimdI32 dest, SimdF32 src, KMask k) =>
    VCVTPS2DQ_EvexMemory(dest, src, k, 8);
public void VCVTPS2DQ_Evex512(SimdI32 dest, SimdF32 src, KMask k) =>
    VCVTPS2DQ_EvexMemory(dest, src, k, 16);

void VCVTPS2DQ_EvexRegister(SimdI32 dest, SimdF32 src, KMask k, int kl)
{
    if (kl == 8 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToI32(src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}

Intrinsics

__m128i _mm_cvtps_epi32(__m128d src)
__m128i _mm_mask_cvtps_epi32(__m128i s, __mmask8 k, __m128d a)
__m128i _mm_maskz_cvtps_epi32(__mmask8 k, __m128d a)

__m128i _mm256_cvtps_epi32(__m256d src)
__m128i _mm256_mask_cvtps_epi32(__m128i s, __mmask8 k, __m256d a)
__m128i _mm256_maskz_cvtps_epi32(__mmask8 k, __m256d a)

__m256i _mm512_cvtps_epi32(__m512d a)
__m256i _mm512_cvt_roundps_epi32(__m512d a, const int rounding)
__m256i _mm512_mask_cvtps_epi32(__m256i s, __mmask8 k, __m512d a)
__m256i _mm512_mask_cvt_roundps_epi32(__m256i s, __mmask8 k, __m512d a, const int rounding)
__m256i _mm512_maskz_cvtps_epi32(__mmask8 k, __m512d a)
__m256i _mm512_maskz_cvt_roundps_epi32(__mmask8 k, __m512d a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#I - Invalid operation.
#P - Inexact result.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.