Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`NP 0F 5A /r` `CVTPS2PD xmm1, xmm2/m64`	`rm`	Invalid	Valid	Valid	`sse2`	Convert packed single-precision floating-point values from xmm2/m64 into packed double-precision floating point values. Store the result in xmm1.
Opcode: `NP 0F 5A /r` Mnemonic: `CVTPS2PD xmm1, xmm2/m64` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert packed single-precision floating-point values from xmm2/m64 into packed double-precision floating point values. Store the result in xmm1.
`VEX.128.NP.0F.WIG 5A /r` `VCVTPS2PD xmm1, xmm2/m64`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed single-precision floating-point values from xmm2/m64 into packed double-precision floating point values. Store the result in xmm1.
Opcode: `VEX.128.NP.0F.WIG 5A /r` Mnemonic: `VCVTPS2PD xmm1, xmm2/m64` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed single-precision floating-point values from xmm2/m64 into packed double-precision floating point values. Store the result in xmm1.
`VEX.256.NP.0F.WIG 5A /r` `VCVTPS2PD ymm1, xmm2/m128`	`rm`	Invalid	Valid	Valid	`avx`	Convert packed single-precision floating-point values from xmm2/m128 into packed double-precision floating point values. Store the result in ymm1.
Opcode: `VEX.256.NP.0F.WIG 5A /r` Mnemonic: `VCVTPS2PD ymm1, xmm2/m128` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert packed single-precision floating-point values from xmm2/m128 into packed double-precision floating point values. Store the result in ymm1.
`EVEX.128.NP.0F.W0 5A /r` `VCVTPS2PD xmm1 {k1}{z}, xmm2/m64/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed single-precision floating-point values from xmm2/m64/m32bcst into packed double-precision floating point values. Store the result in xmm1.
Opcode: `EVEX.128.NP.0F.W0 5A /r` Mnemonic: `VCVTPS2PD xmm1 {k1}{z}, xmm2/m64/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed single-precision floating-point values from xmm2/m64/m32bcst into packed double-precision floating point values. Store the result in xmm1.
`EVEX.256.NP.0F.W0 5A /r` `VCVTPS2PD ymm1 {k1}{z}, xmm2/m128/m32bcst`	`erm`	Invalid	Valid	Valid	`avx512-f` `avx512-vl`	Convert packed single-precision floating-point values from xmm2/m128/m32bcst into packed double-precision floating point values. Store the result in ymm1.
Opcode: `EVEX.256.NP.0F.W0 5A /r` Mnemonic: `VCVTPS2PD ymm1 {k1}{z}, xmm2/m128/m32bcst` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f`, `avx512-vl` Convert packed single-precision floating-point values from xmm2/m128/m32bcst into packed double-precision floating point values. Store the result in ymm1.
`EVEX.512.NP.0F.W0 5A /r` `VCVTPS2PD zmm1 {k1}{z}, ymm2/m256/m32bcst{sae}`	`erm`	Invalid	Valid	Valid	`avx512-f`	Convert packed single-precision floating-point values from ymm2/m256/m32bcst into packed double-precision floating point values. Store the result in zmm1.
Opcode: `EVEX.512.NP.0F.W0 5A /r` Mnemonic: `VCVTPS2PD zmm1 {k1}{z}, ymm2/m256/m32bcst{sae}` Encoding: `erm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert packed single-precision floating-point values from ymm2/m256/m32bcst into packed double-precision floating point values. Store the result in zmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`erm`	`full`	`ModRM.reg[w]`	`ModRM.r/m[r]`

Description

The (V)CVTPS2PD instruction converts two, four, or eight single-precision floating-point values from the source operand into double-precision floating point values. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void CVTPS2PD(SimdF64 dest, SimdF32 src)
{
    dest[0] = ConvertToF64(src[0]);
    dest[1] = ConvertToF64(src[1]);
    // dest[4..] is unmodified
}

void VCVTPS2PD_Vex(SimdF64 dest, SimdF32 src, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = ConvertToF64(src[n]);
    dest[kl..] = 0;
}
public void VCVTPS2PD_Vex128(SimdF64 dest, SimdF32 src) =>
    VCVTPS2PD_Vex(dest, src, 4);
public void VCVTPS2PD_Vex256(SimdF64 dest, SimdF32 src) =>
    VCVTPS2PD_Vex(dest, src, 8);

void VCVTPS2PD_EvexMemory(SimdF64 dest, SimdF32 src, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF64(EVEX.b ? src[0] : src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPS2PD_Evex128Memory(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexMemory(dest, src, k, 4);
public void VCVTPS2PD_Evex256Memory(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexMemory(dest, src, k, 8);
public void VCVTPS2PD_Evex512Memory(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexMemory(dest, src, k, 16);

void VCVTPS2PD_EvexRegister(SimdF64 dest, SimdF32 src, KMask k, int kl)
{
    if (kl == 8 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = ConvertToF64(src[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VCVTPS2PD_Evex128Register(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexRegister(dest, src, k, 4);
public void VCVTPS2PD_Evex256Register(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexRegister(dest, src, k, 8);
public void VCVTPS2PD_Evex512Register(SimdF64 dest, SimdF32 src, KMask k) =>
    VCVTPS2PD_EvexRegister(dest, src, k, 16);

Intrinsics

__m128i _mm_cvtps_pd(__m128d src)
__m128i _mm_mask_cvtps_pd(__m128i s, __mmask8 k, __m128d a)
__m128i _mm_maskz_cvtps_pd(__mmask8 k, __m128d a)

__m128i _mm256_cvtps_pd(__m256d src)
__m128i _mm256_mask_cvtps_pd(__m128i s, __mmask8 k, __m256d a)
__m128i _mm256_maskz_cvtps_pd(__mmask8 k, __m256d a)

__m256i _mm512_cvtps_pd(__m512d a)
__m256i _mm512_cvt_roundps_pd(__m512d a, const int rounding)
__m256i _mm512_mask_cvtps_pd(__m256i s, __mmask8 k, __m512d a)
__m256i _mm512_mask_cvt_roundps_pd(__m256i s, __mmask8 k, __m512d a, const int rounding)
__m256i _mm512_maskz_cvtps_pd(__mmask8 k, __m512d a)
__m256i _mm512_maskz_cvt_roundps_pd(__mmask8 k, __m512d a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#I - Invalid operation.
#P - Inexact result.

Other Exceptions

VEX Encoded Form: See Type 3 Exception Conditions.
EVEX Encoded Form: See Type E3 Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.