Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`F2 0F 2A /r` `CVTSI2SD xmm1, r/m32`	`rm`	Invalid	Valid	Valid	`sse2`	Convert a doubleword integer from r/m32 into a scalar double-precision floating-point value. Store the result in xmm1.
Opcode: `F2 0F 2A /r` Mnemonic: `CVTSI2SD xmm1, r/m32` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse2` Convert a doubleword integer from r/m32 into a scalar double-precision floating-point value. Store the result in xmm1.
`F2 REX.W 0F 2A /r` `CVTSI2SD xmm1, r/m64`	`rm`	Invalid	N/E	Valid	`sse2`	Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Store the result in xmm1.
Opcode: `F2 REX.W 0F 2A /r` Mnemonic: `CVTSI2SD xmm1, r/m64` Encoding: `rm` Validity (16/32/64 bit): invalid, N/E, valid `CPUID` Feature Flag(s): `sse2` Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Store the result in xmm1.
`VEX.LIG.F2.0F.W0 2A /r` `VCVTSI2SD xmm1, xmm2, r/m32`	`rvm`	Invalid	Valid	Valid	`avx`	Convert a doubleword integer value from r/m32 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
Opcode: `VEX.LIG.F2.0F.W0 2A /r` Mnemonic: `VCVTSI2SD xmm1, xmm2, r/m32` Encoding: `rvm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Convert a doubleword integer value from r/m32 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
`VEX.LIG.F2.0F.W1 2A /r` `VCVTSI2SD xmm1, xmm2, r/m64`	`rvm`	Invalid	Invalid	Valid	`avx`	Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
Opcode: `VEX.LIG.F2.0F.W1 2A /r` Mnemonic: `VCVTSI2SD xmm1, xmm2, r/m64` Encoding: `rvm` Validity (16/32/64 bit): invalid, invalid, valid `CPUID` Feature Flag(s): `avx` Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
`EVEX.LLIG.F2.0F.W0 2A /r` `VCVTSI2SD xmm1, xmm2, r/m32`	`ervm`	Invalid	Valid	Valid	`avx512-f`	Convert a doubleword integer from r/m32 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
Opcode: `EVEX.LLIG.F2.0F.W0 2A /r` Mnemonic: `VCVTSI2SD xmm1, xmm2, r/m32` Encoding: `ervm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Convert a doubleword integer from r/m32 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
`EVEX.LLIG.F2.0F.W1 2A /r` `VCVTSI2SD xmm1, xmm2, r/m64{er}`	`ervm`	Invalid	Invalid	Valid	`avx512-f`	Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.
Opcode: `EVEX.LLIG.F2.0F.W1 2A /r` Mnemonic: `VCVTSI2SD xmm1, xmm2, r/m64{er}` Encoding: `ervm` Validity (16/32/64 bit): invalid, invalid, valid `CPUID` Feature Flag(s): `avx512-f` Convert a quadword integer from r/m64 into a scalar double-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3
`rm`	`n/a`	`ModRM.reg[w]`	`ModRM.r/m[r]`
`rvm`	`n/a`	`ModRM.reg[w]`	`VEX.vvvv[r]`	`ModRM.r/m[r]`
`ervm`	`tuple1-fixed`	`ModRM.reg[w]`	`EVEX.vvvvv[r]`	`ModRM.r/m[r]`

Description

The (V)CVTSI2SD instruction converts either a doubleword or quadword integer into a double-precision floating-point value. The result is stored in the destination operand.

The VEX and EVEX forms will copy bits 64..127 from the first source operand into the destination. All forms except the legacy SSE ones will zero the upper (untouched) bits. The EVEX form of this instruction does not support memory-fault suppression. The operand size is always 32 bits if not in Long Mode. In other words, VEX.W1 and EVEX.W1 are treated as VEX.W0 and EVEX.W0 (respectively) outside Long Mode.

Operation

public void CVTSI2SD(SimdF64 dest, I32 src)
{
    dest[0] = ConvertToF64(src);
}
public void CVTSI2SD(SimdF64 dest, I64 src)
{
    dest[0] = ConvertToF64(src);
}

public void VCVTSI2SD_Vex(SimdF64 dest, SimdF64 src1, I32 src2)
{
    dest[0] = ConvertToF64(src2);
    dest[1] = src1[1];
    dest[2..] = 0;
}
public void VCVTSI2SD_Vex(SimdF64 dest, SimdF64 src1, I64 src2)
{
    dest[0] = ConvertToF64(src2);
    dest[1] = src1[1];
    dest[2..] = 0;
}

public void VCVTSI2SD_EvexMemory(SimdF64 dest, I32 src2) =>
    VCVTSI2SD_Vex(dest, src2);
public void VCVTSI2SD_EvexMemory(SimdF64 dest, I64 src2) =>
    VCVTSI2SD_Vex(dest, src2);

public void VCVTSI2SD_EvexRegister(SimdF64 dest, SimdF64 src1, I32 src2)
{
    if (EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);
    dest[0] = ConvertToF64(src2);
    dest[1] = src1[1];
    dest[2..] = 0;
}
public void VCVTSI2SD_EvexRegister(SimdF64 dest, SimdF64 src1, I64 src2)
{
    if (EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);
    dest[0] = ConvertToF64(src2);
    dest[1] = src1[1];
    dest[2..] = 0;
}

Intrinsics

__m128d _mm_cvti32_sd(__m128d s, int32_t a)
__m128d _mm_cvtsi32_sd(__m128d a, int32_t b)

__m128d _mm_cvti64_sd(__m128d s, int64_t a)
__m128d _mm_cvtsi64_sd(__m128d s, int64_t a)
__m128d _mm_cvt_roundi64_sd(__m128d s, int64_t a, const int rounding)

Exceptions

SIMD Floating-Point

#XM

#P - Inexact result.

Other Exceptions

VEX Encoded Form: See Type 5 Exception Conditions.
EVEX Encoded Form: See Type E10NF Exception Conditions.

#UD

If VEX.vvvv is not 1111b.
If EVEX.vvvvv is not 11111b.
If (E)VEX.W is 0, and a floating-point exception is raised while CR4.OSXMMEXCPT is 0.