Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
---|---|---|---|---|---|---|
F3 0F 5A /r CVTSS2SD xmm1, xmm2/m32 | rm | Invalid | Valid | Valid | sse2 | Convert a scalar double-precision floating-point value from xmm2/m32 into a scalar single-precision floating-point value. Store the result in xmm1. |
VEX.LIG.F3.0F.WIG 5A /r VCVTSS2SD xmm1, xmm2, xmm3/m32 | rvm | Invalid | Valid | Valid | avx | Convert a scalar double-precision floating-point value from xmm3/m32 into a scalar single-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1. |
EVEX.LLIG.F3.0F.W1 5A /r VCVTSS2SD xmm1 {k1}{z}, xmm2, xmm3/m32{sae} | ervm | Invalid | Valid | Valid | avx512-f | Convert a scalar double-precision floating-point value from xmm3/m32 into a scalar single-precision floating-point value. Merge the upper bits of the result with those in xmm2. Store the result in xmm1. |
Encoding
Encoding | Operand 1 | Operand 2 | Operand 3 | Operand 4 |
---|---|---|---|---|
rm | n/a | ModRM.reg[rw] | ModRM.r/m[r] | |
rvm | n/a | ModRM.reg[w] | VEX.vvvv[r] | ModRM.r/m[r] |
ervm | tuple1-scalar | ModRM.reg[w] | EVEX.vvvvv[r] | ModRM.r/m[r] |
Description
The (V)CVTSS2SD
instruction converts a scalar single-precision floating-point value from the source operand to a scalar double-precision floating-point value. The result is stored in the destination operand.
The VEX and EVEX forms will copy bits 64..127
from the first source operand into the destination. All forms except the legacy SSE one will zero the upper (untouched) bits.
Operation
public void CVTSS2SD(SimdF64 dest, SimdF32 src)
{
dest[0] = ConvertToF32(src[0]);
// dest[1..] is unmodified
}
public void VCVTSS2SD_Vex(SimdF64 dest, SimdF64 src1, SimdF32 src2)
{
dest[0] = ConvertToF32(src2[0]);
dest[1] = src1[1];
dest[2..] = 0;
}
public void VCVTSS2SD_EvexMemory(SimdF64 dest, SimdF64 src1, SimdF32 src2, KMask k)
{
if (k[0])
dest[0] = ConvertToF32(src2[0]);
else if (EVEX.z)
dest[0] = 0;
// otherwise unchanged
dest[1] = src1[1];
dest[2..] = 0;
}
public void VCVTSS2SD_EvexRegister(SimdF64 dest, SimdF64 src1, SimdF32 src2, KMask k)
{
if (EVEX.b)
OverrideRoundingModeForThisInstruction(EVEX.rc);
if (k[0])
dest[0] = ConvertToF32(src2[0]);
else if (EVEX.z)
dest[0] = 0;
// otherwise unchanged
dest[1] = src1[1];
dest[2..] = 0;
}
Intrinsics
__m128 _mm_cvtss_sd(__m128 a, __m128d b)
__m128 _mm_cvt_roundss_sd(__m128 a, __m128d b, const int rounding)
__m128 _mm_mask_cvtss_sd(__m128 s, __mmask8 k, __m128 a, __m128d b)
__m128 _mm_mask_cvt_roundss_sd(__m128 s, __mmask8 k, __m128 a, __m128d b, const int rounding)
__m128 _mm_maskz_cvtss_sd(__mmask8 k, __m128 a,__m128d b)
__m128 _mm_maskz_cvt_roundss_sd(__mmask8 k, __m128 a,__m128d b, const int rounding)
Exceptions
SIMD Floating-Point
#XM
#D
- Denormal operand.#I
- Invalid operation.
Other Exceptions
VEX Encoded Form: See Type 3 Exception Conditions.
EVEX Encoded Form: See Type E3 Exception Conditions.