Opcode | Encoding | 16-bit | 32-bit | 64-bit | CPUID Feature Flag(s) | Description |
---|---|---|---|---|---|---|
F2 0F 2C /r CVTTSD2SI r32, xmm1/m64 | rm | Invalid | Valid | Valid | sse2 | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a doubleword integer. Store the result in r32. |
F2 REX.W 0F 2C /r CVTTSD2SI r64, xmm1/m64 | rm | Invalid | N/E | Valid | sse2 | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a quadword integer. Store the result in r64. |
VEX.LIG.F2.0F.W0 2C /r VCVTTSD2SI r32, xmm1/m64 | rm | Invalid | Valid | Valid | avx | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a doubleword integer. Store the result in r32. |
VEX.LIG.F2.0F.W1 2C /r VCVTTSD2SI r64, xmm1/m64 | rm | Invalid | Invalid | Valid | avx | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a quadword integer. Store the result in r64. |
EVEX.LLIG.F2.0F.W0 2C /r VCVTTSD2SI r32, xmm1/m64{er} | erm | Invalid | Valid | Valid | avx512-f | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a doubleword integer. Store the result in r32. |
EVEX.LLIG.F2.0F.W1 2C /r VCVTTSD2SI r64, xmm1/m64{er} | erm | Invalid | Invalid | Valid | avx512-f | Convert with truncation a scalar double-precision floating-point value from xmm1/m64 into a quadword integer. Store the result in r64. |
Encoding
Encoding | Operand 1 | Operand 2 | Operand 3 |
---|---|---|---|
rm | n/a | ModRM.reg[w] | ModRM.r/m[r] |
erm | tuple1-fixed | ModRM.reg[w] | ModRM.r/m[r] |
Description
The (V)CVTTSD2SI
instruction converts with truncation a scalar double-precision floating-point value from the source operand into either a doubleword or quadword integer. The result is stored in the destination operand.
The EVEX form of this instruction does not support memory-fault suppression. The operand size is always 32 bits if not in Long Mode. In other words, VEX.W1
and EVEX.W1
are treated as VEX.W0
and EVEX.W0
(respectively) outside Long Mode.
Operation
public void CVTTSD2SI(ref I32 dest, SimdF64 src)
{
dest = ConvertToI32(src[0], truncate: true);
}
public void CVTTSD2SI(ref I64 dest, SimdF64 src)
{
dest = ConvertToI64(src[0], truncate: true);
}
public void VCVTTSD2SI_Vex(ref I32 dest, SimdF64 src) =>
CVTTSD2SI(ref dest, src);
public void VCVTTSD2SI_Vex(ref I64 dest, SimdF64 src) =>
CVTTSD2SI(ref dest, src);
public void VCVTTSD2SI_Evex(ref I32 dest, SimdF64 src) =>
CVTTSD2SI(ref dest, src);
public void VCVTTSD2SI_Evex(ref I64 dest, SimdF64 src) =>
CVTTSD2SI(ref dest, src);
Intrinsics
int32_t _mm_cvttsd_i32(__m128d a)
int32_t _mm_cvttsd_si32(__m128d a)
int32_t _mm_cvtt_roundsd_i32(__m128d a, const int sae)
int64_t _mm_cvttsd_i64(__m128d a)
int64_t _mm_cvttsd_si64(__m128d a)
int64_t _mm_cvtt_roundsd_i64(__m128d a, const int sae)
Exceptions
SIMD Floating-Point
#XM
#I
- Invalid operation.#P
- Inexact result.
Other Exceptions
VEX Encoded Form: See Type 3 Exception Conditions.
EVEX Encoded Form: See Type E3NF Exception Conditions.
#UD
- If
VEX.vvvv
is not1111b
. - If
EVEX.vvvvv
is not11111b
.