Divide Packed Single-Precision Floating-Point Values

Encoding

EncodingOperand 1Operand 2Operand 3Operand 4
rmn/aModRM.reg[rw]ModRM.r/m[r]
rvmn/aModRM.reg[rw]VEX.vvvv[r]ModRM.r/m[r]
ervmfullModRM.reg[rw]EVEX.vvvvv[r]ModRM.r/m[r]

Description

The (V)DIVPS instruction divides four, eight, or 16 packed single-precision floating-point values from the first source operand by those in the second. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void DIVPS(SimdF32 dest, SimdF32 src)
{
    dest[0] /= src[0];
    dest[1] /= src[1];
    dest[2] /= src[2];
    dest[3] /= src[3];
    // dest[4..] is unmodified
}

void VDIVPS_Vex(SimdF32 dest, SimdF32 src1, SimdF32 src2, int kl)
{
    for (int n = 0; n < kl; n++)
        dest[n] = src1[n] / src2[n];
    dest[kl..] = 0;
}
public void VDIVPS_Vex128(SimdF32 dest, SimdF32 src1, SimdF32 src2) =>
    VDIVPS_Vex(dest, src1, src2, 4);
public void VDIVPS_Vex256(SimdF32 dest, SimdF32 src1, SimdF32 src2) =>
    VDIVPS_Vex(dest, src1, src2, 8);

void VDIVPS_EvexMemory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k, int kl)
{
    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = src1[n] / (EVEX.b ? src2[0] : src2[n]);
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VDIVPS_Evex128Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexMemory(dest, src1, src2, k, 4);
public void VDIVPS_Evex256Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexMemory(dest, src1, src2, k, 8);
public void VDIVPS_Evex512Memory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexMemory(dest, src1, src2, k, 16);

void VDIVPS_EvexRegister(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k, int kl)
{
    if (kl == 16 && EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    for (int n = 0; n < kl; n++)
    {
        if (k[n])
            dest[n] = src1[n] / src2[n];
        else if (EVEX.z)
            dest[n] = 0;
        // otherwise unchanged
    }
    dest[kl..] = 0;
}
public void VDIVPS_Evex128Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexRegister(dest, src1, src2, k, 4);
public void VDIVPS_Evex256Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexRegister(dest, src1, src2, k, 8);
public void VDIVPS_Evex512Register(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k) =>
    VDIVPS_EvexRegister(dest, src1, src2, k, 16);

Intrinsics

Exceptions

SIMD Floating-Point

#XM
  • #D - Denormal operand.
  • #I - Invalid operation.
  • #O - Numeric overflow.
  • #P - Inexact result.
  • #U - Numeric underflow.
  • #Z - Divide-by-zero.

Other Exceptions

VEX Encoded Form: See Type 2 Exception Conditions.
EVEX Encoded Form: See Type E2 Exception Conditions.