Arch86

Opcode	Encoding	16-bit	32-bit	64-bit	`CPUID` Feature Flag(s)	Description
`F3 0F 5E /r` `DIVSS xmm1, xmm2/m32`	`rm`	Invalid	Valid	Valid	`sse`	Divide the lowest single-precision floating-point value in xmm1 by the same in xmm2/m32. Store the result in xmm1.
Opcode: `F3 0F 5E /r` Mnemonic: `DIVSS xmm1, xmm2/m32` Encoding: `rm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `sse` Divide the lowest single-precision floating-point value in xmm1 by the same in xmm2/m32. Store the result in xmm1.
`VEX.LIG.F3.0F.WIG 5E /r` `VDIVSS xmm1, xmm2, xmm3/m32`	`rvm`	Invalid	Valid	Valid	`avx`	Divide the lowest single-precision floating-point value in xmm2 by the same in xmm3/m32. Store the result in xmm1.
Opcode: `VEX.LIG.F3.0F.WIG 5E /r` Mnemonic: `VDIVSS xmm1, xmm2, xmm3/m32` Encoding: `rvm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx` Divide the lowest single-precision floating-point value in xmm2 by the same in xmm3/m32. Store the result in xmm1.
`EVEX.LLIG.F3.0F.W1 5E /r` `VDIVSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}`	`ervm`	Invalid	Valid	Valid	`avx512-f`	Divide the lowest single-precision floating-point value in xmm2 by the same in xmm3/m32. Store the result in xmm1.
Opcode: `EVEX.LLIG.F3.0F.W1 5E /r` Mnemonic: `VDIVSS xmm1 {k1}{z}, xmm2, xmm3/m32{er}` Encoding: `ervm` Validity (16/32/64 bit): invalid, valid, valid `CPUID` Feature Flag(s): `avx512-f` Divide the lowest single-precision floating-point value in xmm2 by the same in xmm3/m32. Store the result in xmm1.

Encoding

Encoding	Operand 1	Operand 2	Operand 3	Operand 4
`rm`	`n/a`	`ModRM.reg[rw]`	`ModRM.r/m[r]`
`rvm`	`n/a`	`ModRM.reg[rw]`	`VEX.vvvv[r]`	`ModRM.r/m[r]`
`ervm`	`tuple1-scalar`	`ModRM.reg[rw]`	`EVEX.vvvvv[r]`	`ModRM.r/m[r]`

Description

The (V)DIVSS instruction divides a single single-precision floating-point value from the first source operand with the same in the second. The result is stored in the destination operand.

All forms except the legacy SSE one will zero the upper (untouched) bits.

Operation

public void DIVSS(SimdF32 dest, SimdF32 src)
{
    dest[0] /= src[0];
    // dest[1..] is unmodified
}

public void VDIVSS_Vex(SimdF32 dest, SimdF32 src1, SimdF32 src2)
{
    dest[0] = src1[0] / src[2];
    dest[1] = src1[1];
    dest[2] = src1[2];
    dest[3] = src1[3];
    dest[4..] = 0;
}

public void VDIVSS_EvexMemory(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
    if (k[0])
        dest[0] = src1[0] / src2[0];
    else if (EVEX.z)
        dest[0] = 0;
    // otherwise unchanged
    dest[1] = src1[1];
    dest[2] = src1[2];
    dest[3] = src1[3];
    dest[4..] = 0;
}

public void VDIVSS_EvexRegister(SimdF32 dest, SimdF32 src1, SimdF32 src2, KMask k)
{
    if (EVEX.b)
        OverrideRoundingModeForThisInstruction(EVEX.rc);

    if (k[0])
        dest[0] = src1[0] / src2[0];
    else if (EVEX.z)
        dest[0] = 0;
    // otherwise unchanged
    dest[1] = src1[1];
    dest[2] = src1[2];
    dest[3] = src1[3];
    dest[4..] = 0;
}

Intrinsics

__m128d _mm_div_ss(__m128d a, __m128d b)
__m128d _mm_div_round_ss(__m128d a, __m128d b, int)
__m128d _mm_mask_div_ss(__m128d s, __mmask8 k, __m128d a, __m128d b)
__m128d _mm_mask_div_round_ss(__m128d s, __mmask8 k, __m128d a, __m128d b, int)
__m128d _mm_maskz_div_ss(__mmask8 k, __m128d a, __m128d b)
__m128d _mm_maskz_div_round_ss(__mmask8 k, __m128d a, __m128d b, int)

Exceptions

SIMD Floating-Point

#XM

#D - Denormal operand.
#I - Invalid operation.
#O - Numeric overflow.
#P - Inexact result.
#U - Numeric underflow.
#Z - Divide-by-zero.

Other Exceptions

VEX Encoded Form: See Type 3 Exception Conditions.
EVEX Encoded Form: See Type E3 Exception Conditions.